A general DPLL circuit will be briefly explained. FIG. 1 is a block diagram of a DPPL circuit. FIG. 2 is a graph showing an operation example of a digital phase detector (DPD) 1. FIG. 3 is an explanatory diagram of an operation example of a direct digital synthesizer (DDS) 3.
In FIG. 1, a DPLL circuit includes the DPD 1, a digital loop filter (DLF) 2, a slave oscillator 5, an analog PLL or a multiply circuit 6 that generates a phase count clock, and a frequency divider 4 that converts an output frequency into an input frequency. As shown in FIG. 2, the DPD 1 counts the time between a rising edge of a reference clock (REF_CLK) and a rising edge of a feedback clock (FB_CLK), in a high-speed clock. The DPD 1 outputs a difference Δφ (one count, in the case of the example shown in FIG. 2) between this count and a phase count value at a target convergence point. The APLL, or the multiply circuit 6, shown in FIG. 1 generates a high-speed clock for counting.
The DLF 2 averages a phase error detected by the DPD 1, and smoothes the phase error. The DDS 3 generates an output oscillation waveform by combining digital data called a tuning word (TW), using a clock of a fixed oscillator as an oscillation source. The output frequency can be controlled using the TW. The TW corresponds to a control voltage of voltage controlled oscillator (VCO). FIG. 3 shows the operation of the DDS 3 in detail.
As shown in FIG. 3, a phase accumulator sequentially adds tuning words in a cycle of the input clock 5. When the sum exceeds a value 2N  (=2π) which is expressed in a bit length N (=32 bits) of the phase accumulator, the phase accumulator adds up a difference from 0 after an overflow, thereby repeating an update. An output value from the phase accumulator is converted into a sinusoidal wave, using a sinusoidal wave lookup table stored in a memory. A digital output value which is D/A converted into an analog value becomes an output value of the DDS 3.
When a value of a tuning word is large, a slope of the accumulated sum of tuning words becomes large, and a time taken until an overflow is reached becomes short (i.e., the frequency becomes high, and the phase progresses). On the other hand, when a value of a tuning word is small, a slope of the accumulated sum of tuning words becomes small, and a time taken until when an overflow is reached becomes long (i.e., the frequency becomes low, and the phase is delayed). The frequency divider 4 divides an input frequency into 1/N (for example, 8 KHz or 125 μS) that coincides with a frequency (REF_CLK) of the output clock of the DDS 3.
The basic operation of the DPLL is explained below.
(1) The DPD 1 compares the phase of the reference clock with the phase of the feedback clock.
(2) The DLF 2 averages the error signal (value) Δφ output from the DPD 1, and adds the averaged value as a correction value to the TW of the DDS 3.
(3) The DDS 3 controls a DDS output frequency Fout so that the correction value becomes close to the reference clock frequency (REF_CLK).
After the operations (1) to (3) are repeated, the output frequency (i.e., a deviation) of the DDS 3 finally coincides with the frequency (i.e., a deviation) of the reference clock.
The DDS 3 generates an output clock of the frequency corresponding to a control value called a tuning word (TW), based on the reference clock frequency. The output frequency (Fout) is given by the following expression 1.Fout=Fosc×TW/2NA  (Expression 1)
where
Fout denotes an output frequency,
TW denotes a tuning word, and
NA denotes a bit length of the DDS phase accumulator.
Because Fosc and NA are fixed values, Fout can be controlled based on TW.
The “holdover” refers to a state where, when a trouble occurs in the reference clock (REF_CLK), the clock starts to free run in the frequency deviation immediately before the occurrence of the trouble, and thereafter, the operation continues at the precision of the slave oscillator. Therefore, in general, an oven-controlled crystal oscillator (OCXO) having excellent frequency stability is used for the slave oscillator. However, a synchronization signaling transmission (stratum3E) crystal oscillator requires a temperature characteristic plus minus 10 ppb and a most severe standard for the frequency stability for the OCXO during the holdover period.
Conventionally, a DPLL circuit that generates a reference clock to achieve digital network synchronization is used for a transmitter (such as an optical transmitter and a mobile communication device) within the digital synchronization network. In this case, a reference clock source is present at the highest level of the digital synchronization network. Generally, a cesium atomic oscillator, as a primary standard oscillator, is used for the reference clock source.
Each transmitter within the synchronization network includes a synchronization (Synch) unit that generates a clock to be used within the transmitter based on the clock distributed from the reference clock source. A characteristic of the clock generated by the synchronization unit is prescribed in detail for each subordinate stratum in the synchronization network in ITU810 and GR-1244 (Bellcore). The frequency precision during the holdover is also prescribed in ITU810 and GR-1244 (Bellcore).
As described above, the DPLL corrects a DDS control value (i.e., a tuning word: TW), based on a phase error signal between the phase of the reference clock (REF_CLK) and the phase of the feedback clock (FB_CLK), thereby making the “reference clock frequency (deviation)” coincide with the “output frequency deviation of the DDS”. Therefore, when a trouble occurs in the reference clock, a phase error signal cannot be generated, and the DDS control value (TW) cannot be corrected. Consequently, in general, a holdover circuit fixes the DDS control value to a control value immediately before the occurrence of the trouble.
As explained above, according to the conventional technique, while the DDS control value is fixed during the holdover period, the output frequency (Fout) of the DDS 3 depends on the frequency (Fosc) of the slave oscillator 5 as is clear from the expression 1. Therefore, the output frequency of the DPLL during the holdover directly reflects the frequency and temperature characteristics of the slave oscillator 5. In order to solve this problem, a temperature compensator (i.e., a variable delay circuit) is added to the PLL circuit to control the free-running frequency of the PLL circuit, thereby obtaining a highly stable free-running frequency, as disclosed in Japanese Patent Application Unexamined Publication No. 7-240684.
However, this method has a problem in that the temperature compensation operation is limited to the time of detecting a disconnection of the input of the reference clock. In fact, the holdover operation is not limited to the time of detecting a disconnection of the input of the reference clock, and is also necessary at the time of detecting a circuit trouble of the DPD 1, the DLF 2, and the frequency divider 4, and a disconnection of the input of the feedback clock.